1. Field
The present disclosure relates to a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same.
2. Description of the Related Art
In recent years, as semiconductor device applications continue to demand ever higher performance, certain semiconductor chip sizes and package sizes are increasing. With the trend of electronic devices toward slimness, a thickness of a printed circuit board (PCB) on which packages are mounted often needs to be reduced. As a result, when semiconductor packages are mounted on the PCB, a serious warpage of a substrate may be caused. The warpage may cause many flaws, including a short circuit between bonding units or delamination from the substrate when the semiconductor package is mounted.
Semiconductor packaging technologies are advancing to meet requirements for multi-functioning, high capacity and miniaturization. To meet the requirements, system in package (SIP) technologies have been proposed, in which different semiconductor packages are integrated into one package, thereby expanding the capacity and functions of the semiconductor package while greatly reducing the size of the semiconductor package.
One way of the SIP technologies is to stack semiconductor packages to form a package on package (POP) or a stacked package after each individual semiconductor package undergoes discrete packaging and electrical testing. During the stacking, undesirable warpage of various substrates may occur.